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21 Maxim Integrated Jobs
Staff Design Verification Engineer
6-10 years
Bangalore / Bengaluru
1 vacancy
Staff Design Verification Engineer
Maxim Integrated
posted 3mon ago
Job Role Insights
Flexible timing
Key skills for the job
Job Description
Job Responsibilities:
- Verification of complex designs such as accelerators/ datapath IP, processor core subsystems, complex interfaces/ protocols such as DDR/ Ethernet/ USB etc using leading edge methodologies like UVM Formal DV
- Architect the testbench and develop the verification environment in UVM and Formal based verification approaches
- Define testplan, tests and verification methodology for block / sub-system level verification. Work with design team in generating test-plans and closure of code and functional coverage. Integrate the block testbench at sub-system level UVM environment and verify integration. Interact with analog co-sim and firmware team in enabling toplevel chip verification aspects
- Package verification environment for Digital IP for seamless integration into verification flow at different stages of execution
- Evaluate 3rd party IPs on key qualitative aspects such as design quality, robustness of Design Verification (DV) practice, ease of DV environment integration and make recommendations. Establish evaluation flows for home-grown 3rd party IPs for consistent benchmarking of DV evaluation
- Build expertise on complex interfaces, peripherals protocols such as DDR, Ethernet, eMMC/ SD, MIPI, Display Port, HDMI, PCIe, high speed D2D
- Support post-silicon verification activities of the products working with design, product evaluation and applications engineering team
Position Requirements:
- Minimum B.E./ B.Tech degree in Electrical/Electronics/Computer science
- 6 - 10 years experience in design verification with UVM and constrained random, coverage-based verification approaches
- Strong understanding of DV concepts with an eye on developing scalable DV environment architecture that realizes first pass DV success
- Experience with translating Design Verification (DV) requirements such as test plans into a robust DV environment and generate coverage metrics for demonstrating DV convergence
- Adaptability to learn end application/systems and map into smart verification test plans
- Excellent debugging and analytical skills
- Good interpersonal, teamwork and communication skills to logically effectively drive discussions with teams spread geographically
- Knowledge of Assertion based formal verification
- Understanding of standard on-chip interfaces such as APB/AHB/AXI/ Stream protocols is a strong plus
- Knowledge of Processor/SoC architecture and/or DSP fundamentals is a strong plus
- Experience with ASIC/ SoC product DV productization is very desirable
Employment Type: Full Time, Permanent
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Flexible timing
Monday to Friday
No travel
Day Shift
Maxim Integrated Benefits
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