VLSI Verification Engineer - Static Timing Analysis (4-6 yrs)

Job Summary :

We are looking for a highly skilled VLSI Verification Engineer with expertise in various programming languages, VLSI tools, and domain-specific technologies. The ideal candidate will have experience in Static Timing Analysis (STA), UPF, and Power Domain Technology and be proficient in Verification Methodology. You will be responsible for ensuring the quality and performance of complex VLSI designs by leveraging a wide range of languages, tools, and technologies in the verification process.

Key Responsibilities :

- Design, implement, and execute verification strategies for VLSI designs, ensuring high quality and performance.

- Develop verification testbenches and scripts using languages such as Python, Perl, TCL, C, C++, and Shell scripting.

- Perform Static Timing Analysis (STA) to validate the timing and performance of digital circuits.

- Work with UPF (Unified Power Format) and Power Domain technology to ensure power integrity across VLSI designs.

- Utilize tools like Yosys, OpenTimer, ModelSim, Verilator, and Git to perform functional verification and timing validation.

- Collaborate with cross-functional teams to review design specifications and deliverable requirements.

- Debug and troubleshoot complex issues in digital circuits, including functional and timing-related failures.

- Work in Linux and Windows environments, ensuring smooth operation of design and verification tools.

- Integrate verification flows with other tools and workflows to optimize performance and streamline the design verification process.

- Provide documentation for test results, issues identified, and proposed solutions.

- Support the development of automated verification environments to enhance coverage and efficiency.

- Mentor junior engineers and share best practices for verification methodology and tool usage.

Skills & Qualifications :

- Programming Languages : Proficiency in Python, Perl, TCL, Verilog, C, C++, Makefile, and Shell scripting.

- Tools Expertise : Strong experience with Yosys, OpenTimer, ModelSim, Verilator, and Git.

- Domain Knowledge : In-depth understanding of Static Timing Analysis (STA), UPF, Power Domain Technology, and VLSI Verification Methodology.

- Operating Systems : Experience working in both Linux and Windows environments.

- Familiarity with verification methodologies used in the VLSI industry, including functional and timing verification.

- Strong analytical and debugging skills with the ability to troubleshoot complex VLSI designs and verification issues.

- Experience in setting up and using verification and simulation environments for digital designs.

- Excellent communication and documentation skills for reporting findings, improvements, and solutions.

- Ability to work in a collaborative, cross-functional team environment.

Preferred :

- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

- Experience with power-aware verification techniques and low-power design methodologies.

- Familiarity with digital signal processing and high-performance computing systems.

- Knowledge of industry standards in VLSI design and verification.