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129 UST Jobs

Design Verification Engineer

4-7 years

Malaysia, Penang

1 vacancy

Design Verification Engineer

UST

posted 22d ago

Job Role Insights

Flexible timing

Job Description

Key Responsibilities
  • Develop and execute design verification plans to ensure functional correctness and compliance with specifications.
  • Utilize NLP tools to streamline verification processes, such as requirements analysis and test coverage extraction.
  • Perform power-aware simulations and ensure low-power design compliance using UPF (Unified Power Format) standards.
  • Verify designs for USB protocol compliance and functionality through rigorous testing and simulation.
  • Develop and maintain reusable verification environments, including testbenches and test cases, using industry-standard methodologies (e.g., UVM).
  • Collaborate closely with RTL designers, architects, and firmware engineers to debug and resolve design issues.
  • Analyze simulation results, identify design bottlenecks, and provide recommendations for improvement.
  • Drive continuous improvement in verification methodologies and contribute to the development of best practices.
Required Skills and Qualifications
  • Bachelor's or Master's degree in Electrical/Electronic Engineering, Computer Engineering, or a related field.
  • 4+ years of professional experience in design verification for complex semiconductor systems.
  • Hands-on experience with:
    • NLP techniques for enhancing verification workflows.
    • UPF (Unified Power Format) for low-power design verification.
    • Power-aware simulation methodologies.
    • USB protocol verification.
  • Strong understanding of verification methodologies, including UVM or equivalent.
  • Proficiency in hardware description and verification languages, such as SystemVerilog or Verilog.
  • Excellent problem-solving, debugging, and analytical skills.
  • Strong communication and collaboration skills, with the ability to work effectively in cross-functional teams.
Preferred Skills
  • Experience with scripting languages (Python, Perl, etc.) for automation.
  • Familiarity with EDA tools for simulation and verification.
  • Knowledge of other standard protocols (e.g., PCIe, Ethernet) is a plus.

Employment Type: Full Time, Permanent

Read full job description

Prepare for Design & Verification Engineer roles with real interview advice

Top UST Design & Verification Engineer Interview Questions

Q1. Nth Prime Number Problem Statement Find the Nth prime number given a number N. Explanation: A prime number is greater than 1 and is not the ... read more
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What people at UST are saying

5.0
 Rating based on 1 Design & Verification Engineer review

Likes

Good working culture

  • Skill development - Good
  • +4 more
Dislikes

Less clients for vlsi as of dec 2024

  • Salary - Poor
Read 1 Design & Verification Engineer review

Design & Verification Engineer salary at UST

reported by 9 employees with 1-3 years exp.
₹3.3 L/yr - ₹10 L/yr
At par with the average Design & Verification Engineer Salary in India
View more details

What UST employees are saying about work life

based on 4.4k employees
77%
89%
69%
91%
Flexible timing
Monday to Friday
No travel
Day Shift
View more insights

UST Benefits

Work From Home
Health Insurance
Cafeteria
Soft Skill Training
Team Outings
Job Training +6 more
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