Job Description
Location: Bangalore, India
Experience: 3-7 Years
Joining Date:
2 - 4 Weeks
Roles & Responsibilities:
Custom layout development on block level to Top level I/O layout for GPIO,
HSTL, HCSL, VTMON, LVCMOS, DDR, LVDS etc.
Need knowledge on Latchup, ESD and EM.
Exposure to lower nodes N3E, 5nm etc.
Skills :
LVS/DRC/ERC/Litho Checks/Antenna/ESD-LU/Density etc. Should possess good knowledge
on CMOS functionality, CMOS fabrication process, foundries and challenges in latest
technology nodes.
Well experienced in using industry standard EDA tools like Cadence Virtuoso, Mentor
Graphics
Caliber etc.
Good problem solving and logical reasoning skills.