Lead Verification Engineer (8-10 yrs)

Job Title : Lead Verification Engineer

Location : Hyderabad/Ahmedabad/Bangalore

Position : Full Time

Job Description :

Responsibilities :

- Looking for a lead with 8+ years of experience and should have managed a team of 3-12 engineers while managing deliverables.

- Must have expertise in ASIC verification methodologies and ASIC design flow.

- Experience working of SV and UVM methodology and knowledge of at least one industry standard protocols like Ethernet, PCIe, MIPI, USB, AXI, RISC-V, AMBA, DDR or similar is required, must have executed at-least 2 SoC Verification projects.

- Experience in any of the listed : UVM, formal verification, mixed-signal simulations, power-aware simulations.

- Experience in setting up and debugging functional and/or gate-level simulations.

- Experience in translating functional requirements into verification plans.

- Experience in developing verification environment and regression setup.

- Coverage analysis and closure.

- Worked on SoC level testbench and verification environment Testbench architecture, coding and good understanding of design issues in RTL Testbench generation, testvector creation, simulations, gate level simulations

- Hands on with System Verilog and Assertion based verification methodology

- Atleast 2years of experience on HVL (System Verilog, Vera, Specman, E, VMM, OVM, UVM)

- Should be able to work independently and able to guide others

The role requires this person to be the point of contact for handling and resolving technical queries for other engineers in the team. Committed and passionate for technical work.