Design Engineer II Synthesis

Blaize provides a full-stack programmable processor architecture suite and low code/no-code software platform that enables AI processing solutions for high performance computing at the network s edge and in the data center. Blaize solutions deliver real-time insights and decision-making capabilities at low power consumption, high efficiency, minimal size, and low cost. Blaize has raised over $330 million from strategic investors such as DENSO, Mercedes-Benz AG, Magna, and Samsung and financial investors such as Franklin Templeton, Temasek, GGV, Bess Ventures, BurTech LP LLC, Rizvi Traverse, and Ava Investors. Headquartered in El Dorado Hills (CA), Blaize has more than 200 employees worldwide with teams in San Jose (CA), Cary (NC), and subsidiaries in Hyderabad (India), Leeds and Kings Langley (UK), and Abu Dhabi (UAE).

JOB DESCRIPTION

As a member of Hardware Power Team, the Engineer will be responsible for RTL Power Optimization, Netlist Power Analysis and Optimization on novel machine learning/visual processor chips in advanced nodes.

• BE/BTech in Computer Science or Electronics or Electrical
• 2 5 years experience

• Good understanding of Timing constraints.
• Experience with RTL Synthesis using tools like Design Compiler (DC), Genus.
• Experience in low power design, tools and methodologies including power intent UPF specifications is beneficial.
• Good understanding of ASIC Design & Physical Design Methodologies, Timing Constraints is beneficial.