Design For Test Engineer ( DFT )

About Us:
Silcosys Solutions Private Limited is a pioneer in semiconductor innovation, committed to delivering cutting-edge analog design solutions that power the future of technology. If you are eager to work on impactful projects and advance your expertise, we invite you to join our dynamic team.

Job Description:
As a DFT Engineer, you will be responsible for developing and implementing Design for Test methodologies for complex VLSI designs. You will ensure the testability and manufacturability of our products by working closely with design, verification, and physical design teams, while employing state-of-the-art techniques to optimize coverage, cost, and performance.

Responsibilities:
1. Develop and implement DFT architectures and strategies for complex SoC designs.
2. Insert and verify DFT features such as scan chains, Built-In Self-Test (BIST) for memory and logic, and boundary scan (IEEE 1149.1/1149.6).
3. Perform ATPG (Automatic Test Pattern Generation) and analyze coverage metrics to ensure high fault coverage.
4. Collaborate with RTL designers to ensure seamless integration of DFT features into the design.
5. Debug and resolve test-related issues in simulation, silicon validation, and production.
6. Work closely with the physical design team to implement scan and clock constraints for timing closure.
7. Optimize test time, power, and cost without compromising coverage and quality.
Participate in silicon bring-up and post-silicon validation activities.
8. Generate and maintain DFT documentation, including test plans, methodologies, and results.

Requirements:
1. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field.
2. 2-10 years of experience in DFT for VLSI designs.
Strong knowledge of DFT methodologies, including scan insertion, BIST, and ATPG.
3. Experience with EDA tools such as Synopsys Tetramax/DFTMax, Cadence Modus, or Mentor Tessent.
Proficiency in

4. Verilog/SystemVerilog and scripting languages (Python, TCL, Perl).
5. Solid understanding of STA concepts and constraints related to DFT.
6. Experience in debugging silicon and ATE test patterns.
Knowledge of test standards like IEEE 1149.x (JTAG) and 1500.
7. Excellent problem-solving skills and ability to work in a collaborative environment.

Preferred Qualifications:
1. Experience with low-power DFT techniques.
2. Familiarity with fault diagnosis and yield improvement methodologies.
3. Exposure to advanced nodes (7nm, 5nm, or below) and FinFET technologies.
4. Knowledge of machine learning or AI techniques for test optimization.
5. Hands-on experience with multi-core and hierarchical DFT architectures.

Why Join Us?
1. Be part of a team driving innovation in the semiconductor industry.
2. Work on challenging and impactful projects in a supportive environment.
3. Opportunities for career advancement and skill development.
4. Competitive salary and comprehensive benefits.

How to Apply:
If this role excites you, submit your updated resume at info@silcosys.com and any relevant project portfolios today. Join Silcosys Solutions Private Limited and shape the future of analog design!