Physical Design Engineer

As a Physical Design Engineer, you will be responsible for implementing and optimizing physical designs for high-performance VLSI systems. You will work on a wide range of tasks, including synthesis, placement, routing, and timing closure, ensuring that our designs meet stringent power, performance, and area (PPA) requirements.

Responsibilities:
1. Perform RTL-to-GDSII implementation, including synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off.
2. Optimize designs for PPA while adhering to design constraints and manufacturing requirements.
3. Conduct static timing analysis (STA), power analysis, and physical verification (DRC/LVS).
Collaborate with RTL design, verification, and DFT teams to ensure seamless integration and sign-off.
4. Debug and resolve issues related to timing, signal integrity, and power.
5. Drive closure of physical verification issues such as DRC, LVS, and ERC.
6. Implement low-power design techniques, including power gating, multi-Vt optimization, and dynamic voltage scaling.
7. Work closely with EDA tool vendors to improve design flows and methodologies.
8. Generate and maintain comprehensive documentation for physical design flows and guidelines.

Requirements:
1. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field.
2. 310 years of experience in physical design for VLSI systems.
3. Proficiency in physical design tools such as Cadence Innovus, Synopsys ICC2, or Mentor Calibre.
4. Strong knowledge of STA tools like PrimeTime, Tempus, or equivalent.
5. Experience with advanced process nodes (e.g., 7nm, 5nm, or below) and FinFET technologies.
6. Expertise in low-power design techniques and methodologies.
Solid understanding of DRC/LVS and parasitic extraction.
7. Familiarity with scripting languages (Python, TCL, Perl) for flow automation.
8. Excellent problem-solving skills with the ability to debug and resolve complex physical design challenges.
9. Strong communication and collaboration skills to work effectively in cross-functional teams.

Preferred Qualifications:
1. Hands-on experience with hierarchical design flows and methodologies.
2. Knowledge of 3D IC and advanced packaging technologies.
3. Familiarity with machine learning or AI applications in physical design optimization.
4. Exposure to hardware security aspects in physical design.