CPU Design Verification - Sr Engineer

Job Area: Engineering Group, Engineering Group > Hardware Engineering

General Summary:

Qualcomm is hiring strong DV engineers to verify high performance and low power CPUs in Bangalore. Please forward your profiles if you meet the requirement.

Roles and Responsibilities

o Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling.

o Work closely with design/verification teams within CPU to develop comprehensive test plan.

o Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus.

o Verify power intent through use of methodologies like UPF.

o Work closely with system architects, software teams and Soc team to validate system use cases.

o Work closely with emulation team to enable verification on emulators and FPGA platforms.

o Debug and triage failures in simulation, emulation and/or Silicon.

Minimum Qualifications:

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

o BE/BTech degree in CS/EE with 3+ years experience.

o Experience in power management verification.

o Implementation of assembly and C language embedded firmware.

o Experience in C/C++, scripting languages, Verilog/system Verilog.

o Strong understanding of power management features in CPUs and CPU based Socs.

o Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc.

Preferred Requirements:

o Good Understanding of CPU architectures and CPU micro-architectures.

o In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture

o Experience with advanced verification techniques such as formal and assertions is a plus

o Knowledge and verification experience in DFT and structural debug concepts and methodologies:JTAG, IEEE1500, MBIST, scan dump, memory dump is a plus

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