Dft Design Engineer

Mirafra Technologies Hiring DFT Engineers:

Experience - 3 to 10 years

Notice Period - 0 to 90 days (30 days or lesser notice period will be preferred 1st)

Location - Bangalore

Please find the Job Description Below:

• 3+ years of relevant work experience in DFT.
• Good at Scan and ATPG. Hands on experience in various DFT aspects like Scan insertion, MBIST and JTAG, ATPG, Pattern validation at block level as well as Fullchip level.
• Synopsys tools: DFT MAX, TetraMAX OR Cadence tools: RTL Compiler, Encounter Test OR Mentor Graphics tools: Tessent tool chain, TestKompress - Debussy, VCS/Questa/IUS - PT tool from Synopsys .
• Tool Experience - Cadence Modus / Synopsys DFTMax/TetraMax / Mentor/Tessent
• Expertise in coverage improvement techniques
• Experience in - Stuck at, Transition, Deley faults, Bridging fault, IDDQ
• ATPG simulation - with SDF - should possess good debug skills
• Scripting experience - TCL/Shell/Perl/Python
• Tester/ATE Pattern debug.

If Interested, please share your updated resume at sayantikamajumdar@mirafra.com

Thanks and Regards,

Sayantika Majumdar

Senior Talent Acquisition Specialist

Mirafra Technologies

Email - sayantikamajumdar@mirafra.com

Call- +91 - 9007115796