Sr. Synthesis Engineer

We are seeking a highly skilled and experienced Senior Synthesis Engineer to join our dynamic engineering team. The Senior Synthesis Engineer will be responsible for leading and executing the synthesis process in semiconductor design, focusing on optimizing the digital design flow for high-performance, low-power, and area-efficient integrated circuits (ICs). The ideal candidate will have deep expertise in logic synthesis, RTL (Register Transfer Level) design, and experience with industry-standard EDA (Electronic Design Automation) tools, along with strong problem-solving and analytical skills.

As a Senior Synthesis Engineer, you will be instrumental in driving the technical execution of projects, ensuring that designs meet performance, power, area, and timing requirements. You will work closely with design engineers, verification teams, and other cross-functional teams to deliver high-quality synthesis results and contribute to the successful completion of complex semiconductor designs.

Key Responsibilities:

1. Logic Synthesis & Optimization:

• Perform RTL synthesis and optimization for digital designs, ensuring high-quality results in terms of timing, power, and area (TPA).
• Work with design teams to improve and fine-tune RTL code, applying best practices for design efficiency and optimizing for synthesis tools.
• Implement design optimizations, such as technology mapping, retiming, and logic restructuring, to meet performance goals while minimizing power consumption and chip area.
• Perform clock tree synthesis (CTS), static timing analysis (STA), and other synthesis-related tasks to ensure that timing constraints are met.
• Drive innovation in synthesis techniques to improve design flow efficiency and quality, reducing time-to-market for products.

2. Collaboration with Cross-Functional Teams:

• Collaborate closely with RTL designers, backend engineers, and verification teams to ensure seamless integration between synthesis and other stages of the IC design flow.
• Provide technical leadership and mentorship to junior synthesis engineers, helping them navigate complex synthesis challenges.
• Act as a point of contact for synthesis-related issues, providing expertise and solutions to resolve design and implementation challenges.
• Work with verification teams to ensure that synthesized designs meet functional and performance requirements, and assist in debugging any issues that arise during verification.

3. Synthesis Tool & Flow Development:

• Work with industry-standard EDA tools (such as Synopsys Design Compiler, Cadence Genus, or Mentor Graphics) to perform synthesis, timing analysis, and optimization tasks.
• Develop and maintain automation scripts to streamline the synthesis process, enhancing the efficiency and repeatability of design tasks.
• Customize and optimize synthesis flows to meet project-specific requirements, ensuring that design goals are met while adhering to best practices.
• Stay up-to-date with advancements in synthesis tools, methodologies, and emerging technologies, and incorporate these advancements into the design process.

4. Timing Analysis & Optimization:

• Perform static timing analysis (STA) and dynamic timing analysis to ensure the design meets timing constraints across all process corners and operating conditions.
• Work with the timing closure team to perform incremental timing optimization, handle timing violations, and resolve critical paths.
• Drive efforts to achieve timing closure, working closely with the layout team and other engineering teams to resolve timing issues and meet chip specifications.
• Understand the impact of different process technologies on synthesis, timing, and overall design performance.

5. Power & Area Optimization:

• Optimize designs for power, area, and performance trade-offs, utilizing advanced power reduction techniques, such as clock gating, power gating, and multi-Vt (voltage threshold) techniques.
• Drive improvements in power consumption by identifying opportunities for power-efficient designs during synthesis and optimization.
• Analyze and minimize the area footprint of synthesized designs, ensuring the design fits within chip constraints and meets product specifications.

6. Documentation and Reporting:

• Maintain detailed documentation of synthesis flows, optimization strategies, and results for internal reference and cross-team collaboration.
• Provide regular status updates to project managers and stakeholders on synthesis progress, issues, and solutions.
• Ensure that synthesis reports and timing analysis data are clear, concise, and actionable for other engineering teams.

7. Continuous Improvement & Innovation:

• Contribute to the continuous improvement of synthesis methodologies, tools, and flows to drive efficiency, quality, and innovation in the design process.
• Research and propose new techniques and tools that can improve synthesis performance, such as machine learning-driven optimization or advanced power-saving techniques.
• Stay up to date with industry trends, academic research, and new methodologies related to synthesis, and incorporate these advancements into ongoing design practices.