Principal Architect / Delivery Manager

Top/Block level implementation from netlist to GDS, Handling timing closure of high frequency blocks, Handling blocks of high instance counts 1M instance and above, Expertise in signoff closure Timing with SI and OCV, Power,IR and Physical Verification at both block and chip level, Understanding constraints and fixing techniques, Understanding SI prevention , fixing methodology and implementation, Proficient in layout edit techniques, Proficient in Synopsys ICC or SoC Encounter or Mentor Olympus and Atoptech tool set., Experience in Design Automation and UNIX system. Experience in Tcl/Tk, PERL is a plus.

• Experience level 10 to 18 years.
• Must possess 10+ years of hands on experience in handling block/chip-top level implementation from Netlist to GDS
• Must possess hands on experience in timing closure and physical verification closure
• Must have handled blocks of sizes 1M instances and above at frequencies higher than 1GHz
• Understand AOCV methodology
• Experience in handling lower tech nodes that include 40nm,28nm, 22nm, 20nm, 14nm, etc
• Must have hands on tapeout experience in lower tech nodes in any of the tools mentioned such ICC or SOC Encounter.
• Must have the ability to think on the spot for quick solutions and work-around at the time of tapeout to hit the schedule on time
• Must possess excellent scripting skills TCL or Perl
• Experience in Synthesis and Formal is a plus
• Excellent verbal and written communication skills are required.
• Must possess excellent debug skills, analytical skills and the ability to work independently.
• Must be highly motivated and possess excellent team spirit