Design Implementation Engineer, Senior

Job Area: Engineering Group, Engineering Group > Hardware Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications:

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.Requirements:

Looking for a highly talented and a technically strong leader with an eye for quality to lead a high performing and talented team of engineers in the implementation domain for Display Sub-System.

Able to handle multiple project execution that are time critical and complex

Able to communicate effectively with all stakeholders across the organization

Able to collaborate with cross functional teams for upholding the best practices and enabling smooth execution

Focus on improving execution efficiency and improve on the optimizations in area, power and performance.

Able to grow the team in terms of technical depth and size as we do more and more projects

Able to innovate and bring fresh ideas

Bachelors or masters degree in engineering with 9-13+ Years of experience.

Should have strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools.

Experience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure.

Experience in all aspects of timing closure for multi-clock domain designs.

Should be familiar with MCMM synthesis and optimization.

Should have good understanding of low-power design implementation using UPF.

Experience with scripting language such as Perl/ Python, TCL.

Experience with different power optimization flows or technique such as clock gating.

Should be able to work independently with design, DFT and PD team for netlist delivery, timing constraints validation

Should be able to handle ECOs and formal verification and maintain high quality matrix

Responsibilities include:

Synthesis, LEC, Low power checks, Memory BIST insertion, Constraints validation.

Development of signoff quality constraints and the development of power intent constraints.

May also include running RTL Lint, CLP, MEMBIST, DFT DRC etc.

TCL script development in addition to running/analyzing/debugging designs.

Hands on with Synopsys DCG/Genus/Fusion Compiler.

Hands on with Synopsys Prime Time including constraint development for complex blocks with multiple clock domains.

Hands on with Cadence Conformal LEC and Cadence Conformal Low Power including UPF development

Experience with either RTL development or Physical Design is also a plus

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