Display Design Verification - Associate Engineer

Excellent Design verification domain expertise of min 8 years upto 12 years.
Develop test strategy, TB architecture and test plan for new IPs/new features
Develop strategies for re-useable, scalable and enhance Sub system level verification environment
Excellent C/System Verilog/Verilog skills to handle C based TB environment
Strong skills in debug, post silicon debug-failure re-creation and root cause analysis
Scripting proficiency - PERL, Python, for developing applicable automation
AMBA, AXI bus protocols
Power intent verification, GLS etc.
Capable of communicating effectively with all stakeholders across the globe
Capable of seeding a new team for new IPs, able to hire and expand the team in expertise and efficiency
Capable of mentoring the team members for their career growth, maintaining diversity in the team, collaborating with other leads and managing multiple parallel projects
Take initiatives to enable various ideas for improving efficiencies.
Good to have:
Image Processing, DSI/DP/HDMI Protocols
Good knowledge of new methodologies, flows and tools to be incorporated.
Formal verification