Turing Design Verification - Sr Lead Engineer

Job Area: Engineering Group, Engineering Group > Hardware Engineering

General Summary:

Our team here works on the Verification of advanced IP's, HW Accelerators and Subsystem for AI/ML/DL Applications

Being part of this team will give you exposure to the design and verification of latest Qualcomm AI/ML/DL IP's/Core

Being a part of the DV Team, you will work on Functional , Formal Power aware and Gate level simulation

Get to work on the latest and cutting-edge tech nodes


Required to work on IP verification and own various DV tasks from Test plan creation, coverage model development, test case writing and coverage closure.

Should be proficient in System-Verilog and scripting language like Shell, Perl . Must have RTL/gate level simulation debug experience.

Should have a working knowledge of bus protocols like AHB/AXI .

Candidates should have 5-8 years experience.

Good in SV, UVM, Assertions, GLS

Solid knowledge of C and Scipting language like python

Working knowledge of bus protocol like AHB/AXI

Minimum Qualifications:
"¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.

OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.