Senior Staff Job Posting Title ASIC RTL Design (Turing) - Engineer

Job Area: Engineering Group, Engineering Group > Hardware Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications:

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.

OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.

OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

General Summary:

Experience Required:12+ Years

In this role

You will be interacting closely with the product definition and architecture team.

Developing implementation (microarchitecture and coding) strategies to meet quality, and PPAS (Performance Power Area Schedule) goals for Sub-system.

Define various aspects of the block level design such as block diagram, interfaces, clocking, transaction flow, pipeline, low power etc.

Perform as well as lead a team of engineers on RTL coding for Sub-system/SOC integration, function/performance simulation debug.

Drive Lint/CDC/FV/UPF checks to ensure design quality.

Develop Assertions as part of white-box testing-coverage.

Work with stakeholders to discuss the right collateral quality and identify solutions/workarounds.

Work towards delivering with key design collaterals (timing constraints, UPF etc.).

Desired Skillset:

Good understanding of low power microarchitecture techniques and AI/ML systems.

Thorough knowledge of Computer system architecture, including design aspects of AI/ML designs.

Experience in high performance design techniques and trade-offs in a Computer microarchitecture.

Good understanding of principals of NoC Design

Define Performance (Bandwidth, Latency) and Bus transactions sizing based on usecases across Voltage/Frequency corners

Working with Power and Synthesis teams on usecases, dynamic power and datapath interactions

Knowledge of Verilog / System Verilog. Experience with simulators and waveform debugging tools

Working with SOC DFT and PD teams as part of collaterals exchanges

Knowledge of logic design principles along with timing and power implications.

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