GPU Design Verification Engineers (Multiple Levels )

Job Area: Engineering Group, Engineering Group > Hardware Engineering

General Summary:

Qualcomm is a company of inventors that unlocked 5G, ushering in an age of rapid acceleration in connectivity and new possibilities. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform its potential into world-changing technologies and products. Qualcomm GPU is an industry-leading solution which is driving the benchmarks in mobile computing industry and the future of mobile AR/VR.

Selected candidates will be part of the GPU HW team which is passionate about developing and delivering the best GPU Cores for all Qualcomm Snapdragon SOC products.

Minimum Qualifications:

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.

OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

 

GPU Functional Verification Engineer 
In the role of GPU Functional Verification Engineer, your project responsibilities will include the following,

Develop deep understanding of 3-D Graphics hardware pipeline, feature sets, data paths, block functionalities & interfaces

Strategize, brainstorm, and propose a DV environment, develop test bench, own test plan, debug all RTL artefacts, and achieve all signoff matrices

Engage with EDA vendors, explore new and innovative DV methodologies to push the limits of sign off quality

Collaborate with worldwide architecture, design, and systems teams to achieve all project goals

Currently, we are looking for candidates who can match one or more of the profiles listed below,

Strong knowledge of UVM based System Verilog TB Knowledge of GPU pipeline design is a plus, not mandatory Proficiency with formal tools- working knowledge of Property based FV is a plus, not mandatory Strong communication skills (both written and verbal) Most importantly, ability to learn, improve and deliver

The pre-Si verification team in Bangalore is currently heavily involved in the following

UVM/SV based constrained random test bench for functional verification

Subsystem level TB for complete GPU workload analysis and compliance

Emulation platforms to analyze performance and pipeline bottlenecks

Formal tools- both for reduced time to bug & property based FV sign-off

Power Aware & Gate level simulations to deliver a high-quality GPU implementation

Perl/Python scripts for automation in managing regressions, optimize run time, manage database and bug

 

GPU Functional DV ( Clock/Power) Verification Engineer 
In this role of Graphics Verification Engineer, you will be verifying the Clock and power management module with design features for low power.

The responsibilities will majorly include:

Understanding of GPU power and clock domains with power-up/down sequences

Own end to end DV tasks from coding Test bench and test cases, write assertions, debugging simulations and achieving all coverage goals

Develop test plan to verify sequences and design components for Clock and power management modules.

Explore innovative DV methodologies (formal and simulation ) to continuously push the quality and efficiency of test benches

Successful candidate will be required to collaborate with worldwide design, silicon and architecture teams to achieve all project goals. Hence, we are looking for candidates with strong communication skills.

Understanding of GPU power and clock domains with power-up/down sequences

Strong System Verilog/UVM based verification skills & experience with assertion & coverage-based verification methodology

Experience in formal / static verification methodologies will be a plus

Basic understanding of low power design techniques

Good understanding of design components such as clock gates, level shifters, isolation cells and state retention cells.

Experience with Synopsys NLP (native Low Power) tool.

Experience with scripting languages such as Perl, Python is a plus

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