Technical Lead II - VLSI PD

Physical Design 10+ years of hands-on experience in physical design for complex integrated circuits. Extensive experience with industry-standard physical design tools (e.g., Cadence Innovus, Synopsys IC Compiler, Mentor Graphics, etc.). Deep knowledge of place-and-route, floor planning, clock tree synthesis (CTS), routing, and timing analysis. Expertise in static timing analysis (STA), power analysis, signal integrity, and design rule checks (DRC). Familiarity with process technology nodes ranging from [X nm to Y nm].Experience with advanced physical verification (LVS, DRC, ERC) and design for manufacturability (DFM) techniques. Strong understanding of power, performance, area (PPA) trade-offs and optimization. Proficiency in scripting languages (e.g., Python, TCL, Perl) to automate tasks and develop custom design flows. Proven ability to work cross-functionally with design, verification, and test teams. Excellent verbal and written communication skills, with the ability to communicate complex technical concepts to both technical and non-technical stakeholders. Strong analytical skills with a proven ability to troubleshoot complex physical design issues and optimize solutions. Experience with advanced packaging (e.g., 2.5D, 3D IC, etc. Familiarity with emerging process nodes (e.g., 5nm, 3nm, or beyond).