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Associate III - VLSI
Piktorlabs
posted 3mon ago
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Flexible timing
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Job Description
DFT Engineers
Desired Skills and Experience:
-
B. Tech. / M. Tech. with 4+ years of experience as a DFT Engineer
- In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis.
- Analyze design and propose best compression technique.
- Debug and resolve the DRC issues.
- Work with front end team to provide the solutions and make sure DFT DRCs are fixed.
- Generating high quality manufacturing ATPG test patterns for (SAF) stuck-at, transition fault (TDF), Path Delay fault (PDF) models and through the use of on-chip test compression techniques.
- Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test is required.
- In depth knowledge and hands on experience in MBIST insertion and Memory test validation.
- Expertise in Mentor tools is plus.
Employment Type: Full Time, Permanent
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based on 12 employees
Flexible timing
Monday to Friday
No travel
Day Shift
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