Design Engineer - Memory Subsystem

• Own micro-architecture and RTL development of design modules.

• Micro-architect features to meet performance, power and area requirements.

• Work with HW architects to define critical features.

• Collaborate with verification teams to verify the correctness of implemented features.

• Co-operate with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable.

• Interact with FPGA and S/W teams to prototype the design and ensure that S/W is tested.

• Work on post-silicon verification and debug.

What we need to see:

• BS / MS or equivalent experience.

• 4+ years of design experience.

• Experience in RTL design of complex design units for at least two or three projects.

• Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB).

• Deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up lab debug.

• Expertise in Verilog.

Ways to stand out from the crowd:

• Design experience in memory subsystem or network interconnect IP.

• Good debugging and problem solving skills.

• Scripting knowledge (Python/Perl/shell).

• Leadership experience in leading small 2-3 member teams.

• Good interpersonal skills and ability desire to work as a part of a team.