CPU Verification Engineer

CPU Verification Engineer

About MIPS

We are looking for an experienced CPU Verification Engineer responsible for pre-silicon functional verification of our Coherency Manager, including CPU, Subsystem, and Memory Hierarchy. The role involves designing and verifying custom microprocessor-based systems using cutting-edge verification techniques. You will own verification environments and methodologies to simulate CPU,Cache Subsystem designs and perform verification at various levels within the hierarchy. A solid background in Electronics, Microelectronics, or Computer Science with strong programming skills is essential.

What MIPS offers

• Be a member of a fast-growing team of technologists that are creating the industry`s highest performance RISC-V processors.
• Small teams that are part of a non-compartmentalized structure - you`ll be able to understand and have an impact on the bigger picture.
• A great deal of autonomy, with support from some of the industry`s most experienced CPU engineers.
• An unlimited growth path - with the right skills, you can decide where you want to expand and grow in your role at MIPS.
• The opportunity to learn a great deal about the blossoming RISC-V architecture in cutting edge applications with industry leading customers.
• Meaningful benefits programs and products to our associates and their families.
• A competitive benefits package that includes medical, dental, vision, retirement savings, and paid leave!

More about us

MIPS is well-known as a microprocessor pioneer, having led the way in RISC-based computing to enable faster and more power efficient semiconductors for a wide range of applications from consumer electronics to networking and communications. More than 30 years after the introduction of the original MIPS RISC architecture, MIPS processors have shipped into billions of consumer and enterprise products.

Today, MIPS is once again leading a RISC revolution as we build on our deep roots to accelerate the RISC-V architecture for high-performance applications. We are focused on delivering our first RISC-V products the MIPS eVocore processors, which provide a new level of scalability for high-performance heterogeneous computing. Because of our RISC heritage, deep engineering expertise, and proven technologies, MIPS can accelerate development and deployment of RISC-V based solutions.

Responsibilities

• Own and drive verification environments for microprocessor components.
• Implement best practices and innovative methodologies for robust verification processes.
• Identify and resolve functional and performance issues before silicon production.

Qualifications

• Expertise in functional verification of processors,caches, with proficiency in UVM.
• Deep understanding of computer architecture, including processor core design, cache coherency, IO subsystem, and interrupt architecture.
• Experience verifying multi-processor cache coherency, designs, protocols, and memory subsystems, with hands-on experience in CHI protocol.
• Strong programming skills in SystemVerilog,UVM and Python scripting.
• Experience with Verilog, VHDL, and general computational logic design and verification concepts.
• One full life cycle experience in processor verification, focused on cache coherency.
• Knowledge of system-level architecture including buses such as AXI,ACE,CHI AMBA interconnects.

Additional Qualifications

• Preferred Education and Experience Bachelor`s Degree with 8-12 years of experience, or Master`s Degree with 8-10 years of experience.