Staff Engineer, Scribe Design Non-Array

We are looking for an energetic, ambitious, result-driven individual with strong work ethic and integrity to join us as the Scribe Design Engineer. The Scribe Design Non-Array (SDNA) team is responsible for the design, layout, and verification of CMOS electrical test structures that enable CMOS device development, Compact modeling, Reliability modeling and Fab process monitoring.

In this role you will work with a group of Engineers in India, Japan, and the US. As part of a global team, you will contribute to physical layout, floor planning and verifying through DRC and in-house verification tools. This role will allow you to work on all technology types at Micron.

Specific responsibilities include but not limited to:

• Understand the technology challenges, work with partner groups to provide CMOS Test Structure design and layout solution for N, N+1 and N+2 process technology nodes
• Verify integrity of the TEG design through LVS, DRC, E-simulation, and in-house verification tools
• Attend necessary area and part type meetings to understand the scope and Coordinate activities related to Scribe scheduling, design, improvement and Tape Out.
• Be a strong customer interface to maintain high customer satisfaction with the Scribe Teams service
• Learn and apply Micron Layout methodology for TEG solutions
• Understand the Fab Quality performance of our Scribe designs
• Strive to continuously improve the accuracy and repeatability of our Structures
• Use Metrics and data to drive decisions and improve performance.
• Provide advice and counsel to senior management on significant technical issues related to CMOS TEG design solutions and automation.
• Define and lead complex and multi-disciplinary projects that are critical for SCRIBE Design solutions

Qualifications for this position include:

• Hands on experience and proficiency in EDA tools (Cadence Virtuoso Layout and Schematic Editor, Calibre,Hspice etc)
• Layout and Verification skills in Cadence and Calibre (DRC, LVS)
• Able to run pre and post simulations and analyze the simulations with silicon data.
• Good knowledge of semiconductor device physics, operation, parametric testing and DFM.
• Strong understanding micron memory process
• Good project management skills
• Overview of fab process steps and overall wafer fabrication processes - Familiarity with device characterization is a plus.
• Familiarity with linux/unix system and scripting languages Phyton/Skill is a plus.
• Demonstrated innovative problem-solving skills.
• Willingness to learn new skills and explore unfamiliar concepts.
• Ability to develop and maintain relation with cross-functional teams and partners.
• Good oral and written communication skills to interact with global and local teams.

Education & Experience requirements:

• BE/B.Tech in with at least 10 years of relevant experience
• ME/M.Tech in Electrical or Electronics Engineering or other similar discipline with at least 8 years of relevant experience