DFT Engineer

*Hands on experience with DFT 3-15 Years
*Should have experience in DFT and ATPG activities on SoC designs with expertise in MBIST Planning/Insertion, Partitioning Design for Scan, Scan Insertion
Compression, Wrapper Insertion, ATPG Simulations.
Expertise in handling Flat/Hierarchical SoC designs
Expertise in JTAG, Boundary Scan, STA Constraints creation for DFT modes
*Proven knowledge of VHDL Verilog, RTL design and micro-architecture skills
*Sound knowledge of tools/methodology (Industry standard Simulators and Accelerators, Synthesis, linting checks etc)