Staff Engineer - CAD

Required Skills and Experience :

Bachelors or Masters Degree or equivalent experience in Electronics Engineering, Microelectronics, Software Engineering or a related field. The role of Senior DFT engineer require 5+ years of industry experience with shown ability in DFT of highly sophisticated SOCs :

• Core skills include Scan Codec insertion, Memory BIST and Repair implementation, Logic BIST, ATPG, BSCAN & JTAG (IEEE1149.1 & IEEE1687), Fault Simulation, ATPG Fault models(SAF, TDF, SDD, PDT etc), SDF annotated gate level verification, Scan and Memory Diagnosis.
• Must have experience with Siemens, Synopsys and/or Cadence Cad tools.
• Shall have experience in coding with Verilog, VHDL, C/C++, TCL, Perl and or Python.

Responsibilities -

• Accountable for innovative DFT flow implementation(Scan, MBIST, LBIST & Boundary Scan) at the RTL and Gate level for a given SOC at Hard macro and chip top level.
• Help build flows that generate and validate ATPG patterns using simulations.
• Shall biuld flows that Validate the DFT implementation using RTL and Gate level simulation.
• Work with Multi-functional Teams on STA, Synthesis, LEC, CLP, verification & Validation.
• Support the Silicon bring up activities to guarantee the highest stability of the test patterns/program.
• Chip in to the overall DFT methodology development.

Nice to have Skills/Experience :-

• Shall have Knowledge of IEEE 1149.6, 1500 and 1838.
• Good experience on Hierarchical Scan implementations with core wrapping concepts
• Experience in handling multi-clock domains and low power design implementation.
• Knowledge/Experience on SSN, 2.5D or 3D IC DFT implementation.
• Communicate effusively with multi-functional functional teams in different geographies and time Zones.
• Time management and multi-tasking skills.