Senior Principal Engineer - Physical Design

This position is with ASIC design physical implementation (PD) team part of Custom Compute and Storage (CCS) business unit at Marvell, Bangalore. This team is a part of the global Implementation team that plays a key role in Netlist to GDS implementation, covering Synthesis, P&R, Timing, PV and Power implementation all custom ASICs for all the OEM s, CSSP s. We are looking for strong technical leaders in the domain of physical design having Full-Chip implementation experience on hierarchical designs using industry standard tools.

What You Can Expect

• Take on a Full Chip Lead/Technical Manager role, engaging with customers and stakeholders at a global level to drive technical deliverables and manage dependencies across the design cycle, including DFT, Timing, Front-End (FE), and Power.
• Manage multi-million-gate hierarchical designs, including tasks like sizing, partitioning, chip top clock tree planning, and IO and bump planning. Ensure successful sign-offs for EM/IR, crosstalk, and DFM checks.
• Work on cutting-edge designs using the latest technology nodes (5nm, 3nm, 2nm), collaborating with global teams and demonstrating excellent problem-solving skills.
• Provide technical guidance, review designs, and mentor junior engineers, fostering a collaborative and productive environment.
• Utilize your proficiency in scripting languages such as PERL, TCL, AWK, or Shell to optimize workflows. Excellent written and oral communication skills are essential for effective collaboration and documentation.
• This role is ideal for individuals with strong technical expertise, problem-solving skills, and a passion for leading complex design projects in a global, cutting-edge environment.

What Were Looking For

• Have completed a Bachelor s OR a Masters Degree in Electronics/Electrical/VLSI field and have atleast 18+ years of related professional experience in physical design at Partition/Subsystem/Chip level with a proven track record of successful tape-outs.
• Proficiency in RTL to GDS flows and methodologies, with significant experience in advanced nodes (7nm, 5nm, or below).
• Working knowledge of scripting languages (Perl, TCL, AWK, Python).
• Familiarity with Verilog/VHDL is advantageous.
• Strong interpersonal skills and the ability to work effectively in a collaborative team environment.
• In-depth expertise with industry-standard tools for synthesis, floor planning, placement, clock tree synthesis, routing, and physical verification
• Exceptional verbal and written communication skills