Senior Staff Engineer- Physical Design

Built on decades of expertise and execution, Marvell s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you ll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, automotive, and networking applications.

• In this role based in Hyderabad , you will work with a global team on both the physical design of complex chips as well as the methodology to enable an efficient and robust design process.
• You will be responsible for maintaining, enhancing, and supporting Marvells Place and Route Flow, leveraging industry-standard EDA tools.
• Your tasks will include performing synthesis, place and route, as well as timing analysis and closure on multiple intermediate and complex logic blocks.
• You will play a crucial role in developing and implementing timing and logic ECOs, collaborating closely with the RTL design team to drive modifications that address congestion and timing issues.
• Additionally, your involvement with the global timing team will include debugging and resolving any block-level timing issues encountered at the partition level.
• You will need to work across time zones as a part of multisite project execution.
• This position provides an exciting platform to engage with diverse engineering challenges within a collaborative and innovative environment at Marvell.

• Completed a Bachelor s Degree in Electronics/Electrical Engineering or related fields and have 8-12 years of related professional experience OR a Master s degree and/or PhD in Electronics/Electrical Engineering or related fields with 7+ years of related professional experience.
• In your coursework, you must have completed a digital logic course and projects that involved circuit design, testing, and timing analysis.
• Good understanding of standard Synthesis to GDS flows and methodology.
• Good scripting skills in languages such as Perl, tcl, and Python.
• Good understanding of digital logic and computer architecture.
• Hands-on experience in advanced technology nodes upto 2nm.
• Strong hands-on experience in blocks/subsystem P&R implementation using Cadence Innovus and Synopsys FC.
• Strong experience in block level signoff power, timing, PV closure & debugging skills.
• Good top level and full-chip experience is an added advantage
• Knowledge of Verilog/VHDL.
• Good communication skills and self-discipline contributing in a team environment.
• Ability to independently drive subsystems/IPs P&R and signoff closure working with global teams.
• Ability to mentor juniors and be involved in team development activities.

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