Semiconductor - Senior Verification Engineer

We are seeking multiple experienced Semiconductor Design and Verification Engineer with expertise across multiple domains in the semiconductor lifecycle from Physical Design (PNR) and Test Engineering (DFT) to Digital Verification (DV). The ideal candidate will have a proven track record of working on complex SoC designs, including ARM subsystems, PCIe interfaces, MBIST, Scan Insertion, and ATPG. The role offers a unique opportunity to contribute across the full chip design and verification process, with leadership responsibilities for teams of engineers.

Key Responsibilities

Physical Design (PNR):

Handle full-chip Place and Route (PNR), including timing convergence, congestion analysis, Clock Tree Synthesis (CTS), floor planning, and routing.

Perform timing closure, IR/EM checks, physical verification (DRC/LVS), and sign-off on designs at advanced process nodes (less than 7nm).

Deep understanding of multi-voltage designs, IO ring design, and package-level integration.

Experience with EDA tools and scripting languages (e.g PERL, TCL) for automation in physical design tasks.

Design for Testability (DFT):

Implement MBIST (Memory Built-In Self-Test) and Scan Insertion for SoC and IP block designs.

Develop and execute ATPG (Automatic Test Pattern Generation) for structural and functional fault coverage.

Conduct fault modeling (e.g., stuck-at, transition delay faults) and improve scan test coverage.

Proficient in SDF timing simulations, debug with industry-standard simulators (VCS, NCSim, Xcelium).

Strong knowledge of IR/EM checks and DFM (Design for Manufacturability).

Digital Verification (DV):

Lead SoC-level and IP-level verification efforts for ARM-based designs, ensuring full functionality across subsystems.

Design, develop, and execute testbenches for SoC verification, integrating C code where necessary.

Strong expertise in verifying PCIe interfaces and ensuring compliance with high-speed standards.

Experience with system-level verification, debugging, and test coverage optimization techniques.

Team Leadership:

Lead and mentor a team of 5-8 engineers, overseeing the execution of complex design and verification tasks.

Collaborate with cross-functional teams including design, validation, and product engineering to ensure timely delivery of high-quality results.

Required Skills & Qualifications:

7-10 years of hands-on experience in Physical Design, DFT, and/or Digital Verification in the semiconductor industry.

In-depth knowledge of ARM subsystems, SoC design, and verification methodologies.

Expertise in PNR (Place and Route), CTS, timing closure, DRC/LVS, and physical verification tools.

Strong experience with MBIST, Scan Insertion, ATPG, and fault models like stuck-at and Transition Delay Faults.

Hands-on experience with PCIe and other high-speed interface standards.

Proficient in SDF simulations, timing analysis, and debugging using tools like VCS, NCSim, or Xcelium.

Strong automation skills in PERL, TCL, or equivalent scripting for EDA tool flows.

Leadership experience with a demonstrated ability to manage and guide teams.

Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field.

Preferred Skills:

Experience with lower tech nodes (less than 7nm) in both design and verification.

Familiarity with CADENCE, Synopsys, or Siemens Tessent tools.

Strong communication and problem-solving skills, with a proactive approach to challenges.