Layout Design Engineer

 About The Role : 

You will be part of ACE group within CCG, in the P-Core IP development team driving Intel's latest CPU's in the latest process technology. Your responsibilities will include but not limited to.

Layout design of Datapath and Register Files using semi-automated tools, flows, methodology along with manual polygon edits

Block level/sub-chip level floor-plan, Layout integration, power grid planning, clock routing

Abstract view generation and full-chip assembly

RC extraction, RC aware routing both manual and semi-auto

Coordination with circuit designer

Reliability Verification (EM/SH/IR, etc)

Physical verification (DFM, DRC, LVS, Density, Antenna)

Develop layout design methodologies

 Qualifications 
Qualifications :

You must possess a Bachelor's Degree in E and C or Electrical Engineering or equivalent with at least 4 or more years of experience

Preferred Experience:

Layout design of high speed Datapath or Register file or custom memory

Understanding of Layout design Convergence at Block/Section Level

Basic understanding of timing analysis is plus

Scripting knowledge is plus

Strong verbal and written communication skills

 Inside this Business Group The Core and Client Development Group (C2DG) is a worldwide organization focused on the development and integration of SOCs, Core and critical IPs that power Intel's leadership products, driving most of the Client roadmap for CCG, Delivering Server First Cores that enable continued growth for DCG and invest in future disruptive technologies.