Lead Physical Design Engineer / SoC Full Chip Timing Engineer

In this position, you will be responsible for managing and working on all aspects of SOC Physical design flow, STA and timing closure activities of Intel SoCs in lower technology nodes. Your tasks will include but not limited to:Design and Architecture understanding.

• Interaction with FE/DFT/Verification teams.
• Synthesis, floor planning, placement, routing, clocking, Constraints development. Understanding on synchronous and asynchronous paths, Clock domain crossing issues, deciding timing signoff modes and corners, Design margins.
• Hierarchical timing including IO budgeting for partitions.
• Drive the designs to timing and physical design closure.
• Performs physical design implementation of SOC from RTL to GDS to create a design database that is ready for manufacturing.
• Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, and power and noise analysis.

Education: B.Tech. or M.Tech. in Electrical/Electronics Engineering with 6-12 years' of experience.

Key skills:

• In-depth knowledge and hands-on experience in all aspects of physical design flow in SOC such as synthesis, place, clock tree synthesis, route and signoff. Good understanding and exposure of overall Timing closure cycle in SoC.
• Experience in deep submicron process technology nodes is strongly preferred
• Solid understanding industry standard tools for synthesis, place and route(Fusion Compiler) and timing flows.
• Good scripting skills in TCL/Perl/Shell. Expertise in STA signoff tools (PT).
• Solid understanding of the process and design interactions as they relate to target frequency and interaction with timing paths and resulting leakage and power trade-offs.
• Solid technical and good communication skills.