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Lead Physical Design Engineer / SoC Full Chip Timing Engineer

6-11 years

Bangalore / Bengaluru

Lead Physical Design Engineer / SoC Full Chip Timing Engineer

Intel

posted 6d ago

Job Role Insights

Flexible timing

Job Description

Job Description

In this position, you will be responsible for managing and working on all aspects of SOC Physical design flow, STA and timing closure activities of Intel SoCs in lower technology nodes. Your tasks will include but not limited to:Design and Architecture understanding.

  • Interaction with FE/DFT/Verification teams.
  • Synthesis, floor planning, placement, routing, clocking, Constraints development. Understanding on synchronous and asynchronous paths, Clock domain crossing issues, deciding timing signoff modes and corners, Design margins.
  • Hierarchical timing including IO budgeting for partitions.
  • Drive the designs to timing and physical design closure.
  • Performs physical design implementation of SOC from RTL to GDS to create a design database that is ready for manufacturing.
  • Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, and power and noise analysis.

Qualifications

Education: B.Tech. or M.Tech. in Electrical/Electronics Engineering with 6-12 years' of experience.

Key skills:

  • In-depth knowledge and hands-on experience in all aspects of physical design flow in SOC such as synthesis, place, clock tree synthesis, route and signoff. Good understanding and exposure of overall Timing closure cycle in SoC.
  • Experience in deep submicron process technology nodes is strongly preferred
  • Solid understanding industry standard tools for synthesis, place and route(Fusion Compiler) and timing flows.
  • Good scripting skills in TCL/Perl/Shell. Expertise in STA signoff tools (PT).
  • Solid understanding of the process and design interactions as they relate to target frequency and interaction with timing paths and resulting leakage and power trade-offs.
  • Solid technical and good communication skills.

Employment Type: Full Time, Permanent

Read full job description

Intel Interview Questions & Tips

Prepare for Intel Physical Design Engineer roles with real interview advice

Top Intel Physical Design Engineer Interview Questions

Q1. What are the conditions for an RC circuit to work as an integrator/differentiator Can you derive it with this circuit
Q2. What are second order effects in CMOS. Can you explain each one?
Q3. How would you clear the 7th bit in a 32 bit register
View all 156 questions

What people at Intel are saying

4.3
 Rating based on 16 Physical Design Engineer reviews

Likes

Very good work life balance.

  • Salary - Good
  • +4 more
Dislikes

Learning is slow. You need to take care of your own career growth.

Read 16 Physical Design Engineer reviews

Physical Design Engineer salary at Intel

reported by 118 employees with 2-9 years exp.
₹12.6 L/yr - ₹40 L/yr
185% more than the average Physical Design Engineer Salary in India
View more details

What Intel employees are saying about work life

based on 935 employees
91%
91%
73%
98%
Flexible timing
Monday to Friday
No travel
Day Shift
View more insights

Intel Benefits

Submitted by Company
Learning and career
Flexible Work Options
On-Site Conveniences
Lifestyle
Giving Back
Health Benefits +3 more
Submitted by Employees
Work From Home
Free Transport
Gymnasium
Cafeteria
Health Insurance
Team Outings +6 more
View more benefits

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Intel Bangalore / Bengaluru Office Locations

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Bengaluru Office
136, HAL Old Airport Rd, Kodihalli, Bengaluru, Karnataka 560017, India Bengaluru
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Bengaluru Office
Outer Ring Rd, Adarsh Palm Retreat, Bellandur, Bengaluru, Karnataka 560103, India Bengaluru
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