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ASIC Engineer, Design

2-6 years

Bangalore / Bengaluru

1 vacancy

ASIC Engineer, Design

Facebook

posted 2mon ago

Job Role Insights

Flexible timing

Job Description

Micro-architecture development.
  • RTL development using Verilog, System Verilog and HLS.
  • Lint, CDC, Synthesis, & Power Optimization.
  • Soft and hard IP identification, selection and integration.
  • Collaboration with verification and emulation teams in test plan development and debug.
  • Collaboration with implementation team to close the design on timing and power.
Minimum Qualifications
  • 3+ years of silicon development experience.
  • Experience with Verilog or System Verilog.
  • Experience in one of these skills (minimum 3 years): Micro-architecture and RTL development for complex control and data path IPs, or Experience in SoC Micro-architecture, Design and Integration, or Implementation, Power methodology development.
  • Currently has, or is in the process of obtaining a Bachelors degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta.
Preferred Qualifications
  • Experience in data path development.
  • Experience with Synthesis and Timing Closure.

Employment Type: Full Time, Permanent

Read full job description

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5%
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What Facebook employees are saying about work life

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68%
50%
94%
Flexible timing
Monday to Friday
No travel
Day Shift
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Facebook Benefits

Free Transport
Cafeteria
Free Food
Work From Home
Team Outings
Gymnasium +6 more
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