Physical Design Lead (10-15 yrs)

SALARY : 20LPA - 45LPA

We are recruiting One of Our Indian Based MNC Client

Client - Indian Based MNC Client

Type of Job - Full Time/Direct hire

Type - Hybrid

Notice Period - Not more than 45 Days with serving candidates

Role : Physical Design (PD) Lead

Experience : 10+ Years

Locations : Bangalore

Mandatory Skills : Physical Design Experience

Job Descriptions :

- Tool Proficiency : Proficient in Physical Design tools (ICC2 or Innovus), Static Timing Analysis tools (PrimeTime or Tempus), and Physical Verification tools (Calibre).

- Program Management : Demonstrated experience in leading multiple PD programs with team sizes of 30 or more engineers.

- Full ASIC Flow Expertise : Strong understanding of the full ASIC flow, from front-end RTL to back-end physical implementation and GDSII handoff.

- Leadership and Mentorship : Proven track record of technical leadership.

Job Title : Physical Design (PD) Lead

Job Overview :

As a Physical Design (PD) Lead, you will be responsible for leading the physical design and implementation of complex integrated circuits (ICs), such as SoCs, ASICs, or custom chips. This role involves overseeing the entire physical design flow from synthesis to sign-off, including floorplanning, place and route (P&R), timing closure, power optimization, and DRC/LVS verification. You will work closely with cross-functional teams such as RTL design, verification, and packaging engineers to ensure that the physical design meets performance, power, and area (PPA) goals while adhering to project schedules.

Key Responsibilities :

Physical Design Flow Management :

- Lead the end-to-end physical design flow from RTL to GDSII, including synthesis, floorplanning, place and route, clock tree synthesis (CTS), and timing closure.

- Define and optimize chip floorplans and partitioning to achieve the best possible PPA metrics.

- Oversee timing analysis, signal integrity, and physical verification to ensure design correctness.

Team Leadership & Mentorship :

- Lead and mentor a team of physical design engineers, providing technical guidance and ensuring adherence to best practices.

- Ensure that the team meets project milestones, quality standards, and design constraints.

- Foster a collaborative work environment to solve complex design challenges efficiently.

Optimization for PPA :

- Drive optimization for performance, power, and area (PPA) through rigorous physical design techniques.

- Implement low-power methodologies (e.g., clock gating, multi-Vt libraries) to minimize power consumption.

- Analyze trade-offs between power, performance, and area to meet design goals.

Timing Closure & Analysis :

- Own timing closure, including static timing analysis (STA) and handling signal integrity issues such as crosstalk, IR drop, and electromigration.

- Collaborate with RTL and verification teams to resolve timing violations and other design challenges.

- Perform detailed timing sign-off and generate reports to ensure the design meets all timing constraints.

Physical Verification & Tapeout :

- Lead DRC, LVS, and other physical verification processes to ensure that the design adheres to manufacturing rules.

- Ensure successful chip tapeout by coordinating with foundry partners and resolving any sign-off issues.

- Drive ECO (Engineering Change Order) implementation post-synthesis and post-layout.

EDA Tools & Methodologies :

- Work with cutting-edge EDA tools (Cadence, Synopsys, Mentor Graphics, etc.) for physical design and analysis.

- Continuously improve design methodologies to enhance productivity, automation, and design quality.

- Stay updated on industry trends and adopt new tools and technologies as needed.

Cross-functional Collaboration :

- Collaborate with RTL designers, verification engineers, and packaging teams to ensure that physical design requirements align with overall project objectives.

- Communicate progress, issues, and risks to project management and other stakeholders.

- Provide technical input during design reviews and project planning stages.

Risk Management & Problem-Solving :

- Proactively identify and mitigate risks related to timing, power, area, and manufacturability.

- Lead problem-solving efforts during critical project phases, addressing issues related to design performance or schedule.

Required Skills & Qualifications :

Technical Expertise :

- Extensive experience in physical design for ASICs, SoCs, or custom chips, including synthesis, P&R, CTS, and timing closure.

- Proficiency with EDA tools such as Cadence Innovus, Synopsys ICC2/DC, Mentor Graphics Calibre, or similar.

- Strong understanding of static timing analysis (STA), power analysis, signal integrity, and physical verification.

- Experience with low-power design techniques such as clock gating, multi-Vt design, and power gating.

- Knowledge of DRC/LVS rules, foundry processes, and sign-off criteria for high-volume manufacturing.

Leadership & Management :

- Proven ability to lead and mentor a team of engineers through the physical design process.

- Strong organizational and project management skills, with the ability to prioritize tasks and meet deadlines.

- Excellent problem-solving abilities, with a focus on achieving design goals in terms of PPA and reliability.

Soft Skills :

- Strong communication and interpersonal skills to effectively collaborate with cross-functional teams.

- Ability to present technical information clearly to stakeholders and project managers.

- High attention to detail and strong analytical skills.

Preferred Qualifications :

- Experience with 7nm, 5nm, or other advanced process nodes.

- Knowledge of finFET technology and design challenges at advanced nodes.

- Familiarity with DFT (Design for Test) and DFM (Design for Manufacturability) methodologies.

- Experience with ECO implementation and handling post-layout changes.

- Master's or PhD in Electrical Engineering, Computer Engineering, or a related field.

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