In this role, the Engineer will apply and lead Broadcoms proven design methodology and milestone flow to meet Broadcoms rigorous criteria for achieving Right-first time silicon. Candidate should have very good experience in layout activities of block and SoC level. Should be well experienced in floor-planning, partitioning, placement, clock tree synthesis, route and physical verification.
Responsibilities include, but not limited to:
Deep understanding of SoC for top-down/bottom-up physical design integration in 7nm and lower technologies
Proficient in package co-design concepts Drive Sub-block/partition decisions, floorplan for the best PPAS