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Atindriya Systems

Compare

3.5

based on 3 Reviews

3 Atindriya Systems Jobs

VHDL/Verilog Engineer

Atindriya Systems Pvt Ltd

3.5

based on 3 Reviews

3-6 years

Bangalore / Bengaluru

1 vacancy

VHDL/Verilog Engineer

Atindriya Systems

posted 3+ weeks ago

Job Role Insights

Key skills for the job

Analytical Chemistry Digital Design Troubleshooting VHDL Process Simulation Circuit Designing

+ 2 more

Job Description

Role Description

We are seeking a skilled and experienced VHDL/Verilog Engineer with a minimum of three years of hands-on experience in designing, developing, and testing FPGA and ASIC designs. The ideal candidate will have a strong background in digital design, excellent problem-solving skills, and the ability to work effectively in a team environment.

Key Responsibilities 1. FPGA/ASIC Design

Design, implement, and verify digital circuits using VHDL and/or Verilog.
Develop and maintain FPGA/ASIC designs for various applications.
Perform synthesis, place and route, and timing analysis using industry-standard FPGA tools

2. Simulation and Testing

Write and execute testbenches to verify the functionality of designs.
Use simulation tools to debug and validate designs.
Perform functional and timing simulations.
Utilize advanced testing methodologies to ensure design robustness, including unit testing, integration testing, and system-level testing.
Conduct hardware debugging and validation on FPGA boards.

3. Documentation

Create and maintain design documentation, including specifications, test plans, and user guides.
Prepare detailed reports on design progress and issues.

4. Collaboration

Work closely with hardware and software teams to integrate FPGA/ASIC designs into larger systems.
Participate in design reviews and provide feedback on other team members designs.

5. Optimization and Troubleshooting:

Optimize designs for performance, power, and area.
Troubleshoot and resolve issues related to design, implementation, and testing.

Qualifications

Education : Bachelor s degree in EE, ECE, EEE, CSE or a related field. A Master s degree is a plus.

Experience: At least 3 years of experience in FPGA/ASIC design using VHDL and/or Verilog

Technical Skills:

Proficient in VHDL and/or Verilog HDL.
Extensive experience with FPGA design tools such as Xilinx Vivado, Altera Quartus, and Lattice Diamond.
Knowledge of digital design principles and methodologies.
Proficiency with simulation and verification tools like ModelSim, QuestaSim, and Xilinx ISE Simulator.
Experience with synthesis and timing analysis tools like Synopsys Design Compiler and Cadence Genus.
Expertise in advanced testing methodologies and tools, including automated testing frameworks and hardware-in-the-loop (HIL) testing.
Understanding of hardware description languages and digital circuit design.

Soft Skills: