FPGA RTL Design Engineer/Module Lead

Requirements:

• 2+ years of experience, including successful completion of FPGA based projects
• Coding experience in VHDL and/or Verilog is must
• Experience targeting Xilinx and/or Altera FPGAs required
• Familiarity with tools like Modelsim, Questasim, Xilinx Vivado, Planahead, Altera Quartus etc. is required
• Familiarity with debugging tools like Chipscope, Signal Tap, Logic analyzer, Scope, FPGA editor
• Implementation of designs with multiple clock domains is required
• Thorough understanding of appropriate coding styles for FPGAs, and trade-offs for density and speed
• Experience in RTL implementation of DSP algorithms will be appreciated
• Experience in interfaces like PCIe-Genx, Ethernet, transceivers, DDRx, ADC, DAC, AMBA-AXI, SRAM, USB, UART, I2C, SPI will be appreciated