16 Askexim Services Jobs
3-18 years
Bangalore / Bengaluru, Hyderabad / Secunderabad
Physical Design Engineer - Floor Planning (3-18 yrs)
Askexim Services
posted 2mon ago
Flexible timing
Key skills for the job
Company : a leading Product Engineering company specializing in Semiconductor, Embedded, Artificial Intelligence, and Automotive domains.
Location : Bangalore, Hyderabad
Employment : Full Time. Permanent on-roll job with the company
Notice Period : Immediate to 90 days notice
Experience : 3 to 18 years
Requirement Description :
Qualifications :
- Bachelor's/Master's degree in Electrical Engineering, Computer Engineering, or related field.
- Deep Knowledge of industry standards and practices in Physical Design, including Physical aware synthesis, Floor-planning, and Place & Route
- Experience in developing and implementing Power-grid and Clock specifications
- Strong understanding of all aspects of Physical construction, Integration, and Physical Verification Shown
- Knowledge of Basic SoC Architecture and HDL languages like Verilog to be able with logic design team for timing fixes Power user of industry standard Physical Design & Synthesis tools
- Deep Understanding of scripting languages such as Perl/Tcl, solid understanding of Extraction and STA methodology and tools
- Deep Understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level
Job Description :
- As a Physical Design engineer, you will contribute to all phases of physical design of high-performance design from RTL to delivery of our final GDSII.
- Your responsibilities include but are not limited to Generating block/chip level static timing constraints.
- Build a full chip floor plan including pin placement, partitions, and power grid.
- Develop and validate high-performance low-power clock network guidelines.
- Perform block-level place and route and close the design to meet timing, area, and power constraints.
- Generate and Implement ECOs to fix timing, noise, and EM IR violations.
- Run Physical design verification flow at chip/block level and provide guidelines to fix LVS/DRC violations to other designers.
- Participate in establishing CAD and physical design methodologies for correct construction designs.
- Assist in flow development for chip integration
Functional Areas: R&D
Read full job description3-18 Yrs
Bangalore / Bengaluru, Hyderabad / Secunderabad
1-6 Yrs
2-10 Yrs
Mumbai, Bangalore / Bengaluru