Home
Communities
Companies
- Companies
  
  Discover best places to work
- Compare Companies
  
  Compare & find best workplace
- Add Office Photos
  
  Bring your workplace to life
- Add Company Benefits
  
  Highlight your company's perks
Reviews
- Company reviews
  
  Read reviews for 6L+ companies
- Write a review
  
  Rate your former or current company
Salaries
- Browse salaries
  
  Discover salaries for 6L+ companies
- Salary calculator
  
  Calculate your take home salary
- Are you paid fairly?
  
  Check your market value
- Share your salary
  
  Help other jobseekers
- Gratuity calculator
  
  Check your gratuity amount
- HRA calculator
  
  Check how much of your HRA is tax-free
- Salary hike calculator
  
  Check your salary hike
Interviews
- Company interviews
  
  Read interviews for 40K+ companies
- Campus placements
  
  Interviews questions for 2K+ colleges
- Share interview questions
  
  Contribute your interview questions
Jobs
Awards

WINNERS AWAITED!
- ABECA 2025
  
  WINNERS AWAITED!
  
  AmbitionBox Employee Choice Awards - 4th Edition
- ABECA 2024
  
  AmbitionBox Employee Choice Awards - 3rd Edition
- AmbitionBox Best Places to Work 2022
  
  2nd Edition
- AmbitionBox Best Places to Work 2021
  
  1st Edition

Add office photos

Premium Employer

Advanced Micro Devices

Compare

3.7

based on 257 Reviews

Video summary

227 Advanced Micro Devices Jobs

Full-Chip Floor Planning Lead (SMTS Silicon Design Engineer)

Advanced Micro Devices, Inc

3.7

based on 257 Reviews

4-9 years

Bangalore / Bengaluru

1 vacancy

Full-Chip Floor Planning Lead (SMTS Silicon Design Engineer)

Advanced Micro Devices

posted 6d ago

Job Role Insights

Flexible timing

Key skills for the job

Python Social Work Automation Testing Recruitment Gaming Partnerships

+ 4 more

Job Description

As a Full-Chip Floor Planning Engineer, you will play a crucial role in the physical design and implementation of advanced semiconductor chips. Working closely with RTL designers, physical design teams, and other cross-functional groups, you will be responsible for full-chip floor planning, enabling efficient design layouts, and optimizing the placement of major functional blocks. This position requires a solid understanding of physical design and chip architecture, as well as experience in floor planning tools and methodologies for high-performance and low-power design.

Technical Requirements

Proven experience in top level floor planning/block partition which includes physical partition, pin/feedthrough placements and repeaters assignments.

Experience in SOC floorplan aspects like FullChip clock spine distribution, analog integration, push down macros, GPIOs.

Proficiency in EDA tools such as Cadence, Synopsys ICC, Calibre, etc
Strong scripting skills in Tcl, Perl, or Python for automation
In-depth knowledge of upf, floor planning concepts, including chip partitioning, placement, and routing methodologies.
Experience with power, timing, and area optimization techniques
Familiarity with design rule check (DRC) requirements.

Responsibilities

Lead the floor planning process from RTL to GDSII, optimizing block placement, chip partitioning, and routing feasibility to ensure timing, power, and area constraints are met.
Collaborate with RTL, block-level, and physical design teams to integrate IPs, macros, and other design components efficiently at the top level
Work on area and power optimization techniques to achieve a highly efficient chip layout. Perform what-if analyses to evaluate trade-offs and optimize design parameters.
Interface with architecture, package, and timing teams to align on chip-level requirements and ensure the physical design meets performance and design intent.
Identify potential design issues early in the floor planning process and collaborate with stakeholders to develop and implement mitigation strategies
Develop, enhance, and maintain custom scripts to automate repetitive tasks within the floor planning flow, ensuring efficiency and accuracy.