Design & Verification Engineer salary at Synopsys ranges between ₹8.6
Lakhs
to ₹11
Lakhs
per year for employees with experience between 2 years to 3 years. Salary
estimates are based on
2 latest salaries received
from various employees of Synopsys.
Top skills at Synopsys for Design & Verification Engineer
System Verilog
Communication Skills
RTL Design
Verilog
VHDL
Python
TCL
Medical Coding
UVM
PCIE
Design Verification
Analog
Test Cases
SOC Verification
UVM
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1w (edited)
an associate vice president

Offer Accepted
I was getting 15.2 LPA in my previous org and now i am being offered 29.5 LPA but the designation is 1 position lower than what i was in my previous org. Should i go ahead with the offer or still negotiate on designation.
Protip : i was laid off in my previous org.
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Synopsys Design & Verification Engineer Salary FAQs
What is the notice period for Design & Verification Engineer at Synopsys in New Delhi?
According to AmbitionBox, 100% of the Synopsys Design & Verification Engineers in New Delhi reported a notice period of 15 days or less.This is based on 1 response on AmbitionBox in last 2 years.
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- Synopsys Design & Verification Engineer Salaries in New Delhi
Synopsys Design & Verification Engineer salary in New Delhi ranges between ₹8.6 Lakhs to ₹11 Lakhs. This is an estimate based on latest salaries received from employees of Synopsys.