Designation | Avg Annual Salary | Open Jobs |
---|---|---|
Verification Engineer 0 -
3
years
exp.
(24
salaries) | ₹2.2 L/yr - ₹6 L/yr | |
RTL Design Engineer 2 -
4
years
exp.
(17
salaries) | ₹3.1 L/yr - ₹9.5 L/yr | |
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| ||
Asic Verification Engineer 2 -
4
years
exp.
(16
salaries) | ₹3.3 L/yr - ₹9 L/yr | |
Asic RTL Design Engineer 3 -
4
years
exp.
(9
salaries) | ₹6 L/yr - ₹11 L/yr | |
Starting your career? Discover SmartDV Technologies fresher salaries in India | ||
Design Engineer 0 -
4
years
exp.
(6
salaries) | ₹3 L/yr - ₹4.6 L/yr | |
Asic Design Engineer 1 -
2
years
exp.
(6
salaries) | ₹3.7 L/yr - ₹4.2 L/yr | |
Fpga Engineer 0 -
2
years
exp.
(6
salaries) | ₹3.5 L/yr - ₹4 L/yr | |
Design & Verification Engineer 3 -
5
years
exp.
(5
salaries) | ₹6.4 L/yr - ₹8.6 L/yr | |
Analog Design Engineer 1 -
2
years
exp.
(4
salaries) | ₹3.5 L/yr - ₹4.1 L/yr | |
Associate Project Manager 1 -
2
years
exp.
(3
salaries) | ₹3.8 L/yr - ₹4 L/yr | |
Full Stack Web Developer 1 -
3
years
exp.
(3
salaries) | ₹3 L/yr - ₹6 L/yr | |
Senior Verification Engineer 3 -
4
years
exp.
(3
salaries) | ₹4.3 L/yr - ₹6 L/yr | |
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| ||
Data Analyst 1 -
2
years
exp.
(3
salaries) | ₹3.2 L/yr - ₹4.5 L/yr | |
PCB Design Engineer 5 -
6
years
exp.
(3
salaries) | ₹4.2 L/yr - ₹4.7 L/yr | |
RTL Verification Engineer 1 -
2
years
exp.
(3
salaries) | ₹3.1 L/yr - ₹3.2 L/yr | |
Asic Design Verification Engineer 0 -
3
years
exp.
(3
salaries) | ₹3.7 L/yr - ₹8.5 L/yr | |
Network Engineer 1
year
exp. (AmbitionBox Estimate) | ₹2.5 L/yr - ₹3.2 L/yr | |
Finance Manager 1 -
3
years
exp.
(AmbitionBox Estimate) | ₹9.4 L/yr - ₹12 L/yr | |
Linux System Administrator 5 -
6
years
exp.
(AmbitionBox Estimate) | ₹4.3 L/yr - ₹5.5 L/yr | |
Senior Software Engineer 8 -
10
years
exp.
(AmbitionBox Estimate) | ₹7 L/yr - ₹9 L/yr |
Last Updated: 3 Apr, 2025
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Verification Engineer | ₹2.2 Lakhs to ₹6 Lakhs per year |
RTL Design Engineer | ₹3.1 Lakhs to ₹9.5 Lakhs per year |
Asic Verification Engineer | ₹3.3 Lakhs to ₹9 Lakhs per year |
Asic RTL Design Engineer | ₹6 Lakhs to ₹11 Lakhs per year |
The highest-paying role, Asic RTL Design Engineer, earns between ₹6 Lakhs to ₹11 Lakhs per year. The top 10% of employees earn more than ₹8.6 Lakhs per year, and the top 1% earn over ₹13.8 Lakhs per year. Salaries at SmartDV Technologies can be higher or lower depending on factors such as the specific team, level of experience, and additional benefits like bonuses and stock options.
These salary estimates are based on data from 171 salaries submitted by SmartDV Technologies employees. SmartDV Technologies is rated 2.8 out of 5 stars by its employees on the salary and benefits parameter.
Fresher as a Verification Engineer Salary | ₹2.2 Lakhs to ₹3.8 Lakhs per year |
Fresher as a Design Engineer Salary | ₹3 Lakhs to ₹4 Lakhs per year |
Fresher as a Trainee Design Engineer Salary | ₹3.4 Lakhs to ₹4.3 Lakhs per year |
Fresher as a Engineering Student Salary | ₹3.1 Lakhs to ₹3.9 Lakhs per year |
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