Companies similar to SkandySys Technologies for Design & Verification Engineer
Company name | Avg Annual Salary | Open Jobs |
---|---|---|
![]() Truechip Solutions Design & Verification Engineer Salary
0 - 4 years exp. (19 salaries) | ₹4 L/yr - ₹16.2 L/yr | 2 job openings |
![]() MaxLinear Design & Verification Engineer Salary
2 years exp. (5 salaries) | ₹6 L/yr - ₹8 L/yr | |
Login to view exact salary
| ||
![]() Test and Verification Solutions Design & Verification Engineer Salary
3 - 5 years exp. (5 salaries) | ₹11.3 L/yr - ₹24 L/yr | |
![]() Xilinx Design & Verification Engineer Salary
1 - 2 years exp. (4 salaries) | ₹9 L/yr - ₹16 L/yr | |
AumRaj Design Systems Design & Verification Engineer Salary
0 - 5 years exp. (4 salaries) | ₹12 L/yr - ₹15 L/yr | |
![]() SignOff Semiconductors Design & Verification Engineer Salary
0 - 2 years exp. (4 salaries) | ₹3.5 L/yr - ₹8.9 L/yr | |
Experience wise SkandySys Technologies Design & Verification Engineer salaries
Last Updated: 11 Mar 2023
Experience | Avg Annual Salary |
---|---|
1 year (AmbitionBox Estimate) |
₹1.1
L/yr
- ₹1.4
L/yr
|
Login to view exact salary
| |
2 years (AmbitionBox Estimate) |
₹1.6
L/yr
- ₹2
L/yr
|
Similar Designation salaries in SkandySys Technologies
Discover interview dos and don'ts from real experiences
Top trending discussions








SkandySys Technologies Design & Verification Engineer Salary FAQs
Experience | Average Salary Range |
---|---|
1 year | ₹1.1 Lakhs to ₹1.4 Lakhs per year |
2 years | ₹1.6 Lakhs to ₹2.0 Lakhs per year |
Tell us how to improve this page.
- Home >
- Salaries >
- SkandySys Technologies Salaries >
- SkandySys Technologies Design & Verification Engineer Salaries
SkandySys Technologies Design & Verification Engineer salary
in
India
ranges between ₹1.2
Lakh to ₹2.4
Lakhs with an average annual salary of
₹. Salary estimates are based on
3
SkandySys Technologies latest salaries received from various employees of
SkandySys Technologies.