Asic Design Verification Engineer salary at Marvell Semiconductors ranges between ₹12
Lakhs
to ₹15.4
Lakhs
per year for employees with 1 year of experience. Salary
estimates are based on
1 latest salaries received
from various employees of Marvell Semiconductors.
Similar Designation salaries in Marvell Semiconductors
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Career Growth
2w (edited)
littleiv

·
works at
Capgemini

Tech lead - Tech Mahindra or IBM
I have 2 offers in same location : Need guidance to choose one
1) Tech Mahindra (U4)
Fixed 23.9 Variable 2.6=26.5
No joining bonus
Project details informed already
2)IBM(7B)
Fixed 21.37 + Variable 0-10%
Joining bonus is 1 lakh
Your Responses and thoughts will be appreciated.
Thank you
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Marvell Semiconductors Asic Design Verification Engineer Salary FAQs
How the salary growth look like for a Asic Design Verification Engineer at Marvell Semiconductors in Pune?
The salary growth for a Asic Design Verification Engineer at Marvell Semiconductors in Pune depends on factors such as experience, performance, and promotions. On average, a Asic Design Verification Engineer in Pune can expect the following growth trajectory at Marvell Semiconductors:
and so on.
Experience | Average Salary Range |
---|---|
1 year | ₹12.0 Lakhs to ₹15.4 Lakhs per year |
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- Marvell Semiconductors Asic Design Verification Engineer Salaries in Pune
Marvell Semiconductors Asic Design Verification Engineer salary in Pune ranges between ₹12 Lakhs to ₹15.4 Lakhs. This is an estimate based on latest salaries received from employees of Marvell Semiconductors.