Soc Physical Design-Timing Engineer

Come join Intel's highly regarded Devices Development Group, responsible for creating Client SOCs. We envision the future of computing and design for the next generation of laptop and desktop computers.We are looking for an SoC (System on Chip) Physical Design Engineer, ready to research, design, develop, and test lead Intel designs as we reimagine how to build SOCs at Intel and in the semiconductor industry.

Our

• Driving performance optimization, including co-optimization work with process teams, to create best-in-class designs.
• Physical synthesis, place and route, and clock tree synthesis with Synopsys or Cadence tools.
• Static timing analysis constraint understanding and generation, clock stamping, and timing closure.
• Multiple Power Domain analysis using standard Power Formats UPF or CPF.The ideal candidate should exhibit behavioral traits that indicate:

• Self-motivator with strong problem-solving skills.
• Excellent interpersonal skills, including written, verbal, and presentation communications
• Attention to detail and organizational skills
• Ability to work as part of a team and collaborate in a high-paced atmosphere.

• BS/BTech degree with 3 years of experience, or MS/MTech degree with 1 year of experience, in Electrical Engineering, Computer Engineering, or a related field
• 2+ years of experience in backend design and/or STA in one of the following areas:
• Physical synthesis, place and route, and clock tree synthesis with Synopsys or Cadence tools.
• Static timing analysis constraint understanding and generation, clock stamping, and timing closure.
• Multiple Power Domain analysis using standard Power Formats UPF or CPF

Preferred Qualifications:

• 5+ years of experience in backend design and/or STA.
• Experience with product development and delivery on leading edge process nodes.