Semiconductor Design Engineer 3

Developing and understanding building block schematics and memory schematics.
- Running circuit simulations using spice simulators for DC and transient analysis.
- Deciphering circuit behavior from schematics.
- Familiar with circuit characterization, timing libraries - files and formats, timing arcs.
- Experienced in Verilog MOS switch level models and netlist simulation with zero delay, unit delay, and path delay simulations.
- Knowledge in static timing analysis.
- Conducting gate level simulations with SDF back annotation.
- Debugging SDF annotation issues and ensuring good annotation coverage.
- Understanding latch based designs and their timing requirements.
- Debugging gate level simulation failures and determining the cause of the failures to actual circuits.
- Performing what-if analysis by making changes and ensuring the fix can solve the issue.
- Using System Verilog Assertions to specify expected design behavior.