Staff Verification Engineer

Marvells Optical and Copper Connectivity Business Unit is the industry leading provider of infrastructure solutions to enterprise, data center, service providers, small business, and digital home customers.
The HSC team is a key part of Optical and Copper Connectivity Business Unit that creates Marvell s high-speed copper PHY/Retimer products.
At Marvell, everyone has an important role to play in changing the way tomorrow s enterprise, cloud, automotive, and carrier architectures transform for the better. We move, store, process and secure the world s data with semiconductor solutions designed for our customers current needs and future ambitions.

• Develop and maintain verification environment in UVM (Universal Verification Methodology)
• Define and review verification test plan with architecture team and design team
• Verify the design with directed and constraint random functional parameters
• Maintain regression and debug test failures with designers
• Report and analyze verification coverage of design features and parameters
• Drive the verification to reach coverage target
• Take responsibility in the verification of blocks, sub-systems and top-level environment.

• Masters/Bachelor s degree in Electrical Engineering or related fields and 4+ years of design verification experience.
• Hands-on experience on using Verilog, System Verilog and UVM (Universal Verification Methodology)
• Good scripting skills in languages such as Perl, Tcl, or Python.
• Experience in PCIe and CXL is a plus
• Good verbal and written communication skills in English.

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