Senior Design Verification Engineer - SoC/System Verilog (4-8 yrs)

Job Title : Design Verification Engineer

Experience : 4+ Years Experience

Location : (UK with Vaild VISA),Malaysia,Bangalore and Hyderabad

Job Description :

We are seeking an experienced and highly skilled Senior Design Verification Engineer with a minimum of 4 years of hands-on experience in Design Verification. As a key member of our team, you will play a pivotal role in ensuring the robustness and correctness of our cutting-edge System on Chip designs.

Responsibilities :

- Lead and manage Design Verification efforts for complex projects, ensuring the successful execution of verification plans.

- Develop and implement comprehensive verification strategies, test plans, and test benches for high speed including low-speed peripherals like I2C/I3C, SPI, UART, GPIO, QSPI, and high speed protocols like PCIe, USB

- Collaborate closely with cross-functional teams, architects, designers, and pre/post-silicon verification teams

- Analyze and implement System Verilog assertions and coverage (code, toggle, functional).

- Provide mentorship and technical guidance to junior verification engineers.

- Manage and lead a dynamic team of verification engineers, fostering a collaborative and innovative work environment.

- Ensure verification signoff criteria are met and documentation is comprehensive

- Demonstrate dedication, hard work, and commitment to achieving project goals and deadlines

- Adhere to quality standards, implement good test practices, and contribute to the continuous improvement of verification methodologies.

- Experience with verification tools from Synopsys and Cadence, including VCS and Xsim.

- Integration of third-party VIPs (Verification IP) from Synopsys and Cadence.

Qualifications :

- Bachelor's degree in computer science, Electrical/Electronics Engineering, or related field OR Master's degree in computer science, Electrical/Electronics Engineering, or related field OR PhD in Computer Science, Electrical/Electronics Engineering, or related field.

- 4+ years of hands-on experience in Design Verification.

- Expertise in UVM (Universal Verification Methodology) and System Verilog.

- Prior experience working on IP level and SOC level verification projects.

- Proficient in verification tools such as VCS, Xsim, waveform analyzers, and third party VIP integration (e.g., Synopsys VIPs and Cadence VIPs).

- Hands-on experience USB,Ethernet, PCIe, CXL, MIPI protocols.

- Solid understanding of low-speed peripherals (I2C/I3C, SPI, UART, GPIO, QSPI) and high-speed protocols.

- Proficiency in scripting languages such as shell, Makefile, and Perl

- Strong understanding of processor-based SOC verification, including native, Verilog, System Verilog, and UVM mixed environment.

- Excellent problem-solving, analytical, and debugging skills