Technologist, ASIC Development Engineering

Job Summary:

We are seeking an experienced STA Architect to lead our technical team. The ideal candidate will have extensive experience in Static Timing Analysis, a deep understanding of digital design, and the ability to lead and mentor a team of engineers.

This role requires hands-on expertise in STA tools, methodologies, and a strategic vision to drive the timing closure of complex designs.

Key Responsibilities:

- Lead the STA function and oversee all aspects of timing analysis and closure for ASIC designs.

- Develop and implement STA methodologies and best practices to ensure high-quality design closure.

- Collaborate with cross-functional teams, including IP design, DFT, and verification teams, to address timing challenges and drive design convergence.

- Conduct thorough timing analysis using industry-standard STA tools (e. g. , Synopsys PrimeTime, Cadence Tempus).

- Define and drive timing constraints development and validation processes.

- Provide technical leadership and mentorship to junior engineers, fostering a culture of continuous learning and innovation.

- Work closely with project managers to ensure timely delivery of design milestones and project goals.

- Stay updated with the latest industry trends and advancements in STA methodologies and tools.

- Participate in design reviews, providing expert insights and recommendations to optimize performance and timing.

- Troubleshoot and resolve complex timing issues, utilizing advanced debugging techniques.