Lead Engineer DFT

Will be responsible for Designing and Implementing DFT techniques. (Memory BIST/Scan /On-Chip Compression/At-speed Scan/Test-clocking/Boundary Scan/Analog Testing/Pin-muxing/Logic BIST) on complex SOCs to improve testability. Test Modes implementation and verification, scan insertion including on-chip compression.. Implementing, integrating and verifying memory BIST and boundary scan .

Test vector (Stuck-at/At-speed/Path delay/SDD/IDDQ/Bridging fault) generation with high test coverage and simulations at gate level with timing (SDF). Basic understanding of complete SOC design and flow.Cross functional teams interaction for issue resolution.

Participate in driving new DFT methodology and solutions to improve quality, reliability and in-system test and debug capability. Mentoring new team members. Strong inter personal and communication