DSP / NPU Design Verification Sr Engineer

Job Area: Engineering Group, Engineering Group > Hardware Engineering

General Summary:

Job Summary:

· Position for 5-8 years of experience in

design verification of complex Qualcomm propriety DSP/NPU IP

· DSP team is responsible for delivering high-performance DSP/NPU cores which are at the heart of Qualcomm's multi-tier SoC roadmap targeted for mobile space, AI, Automotive and more.

· Qualcomm is one of the largest fabless semiconductor design companies in the world, generating over $35 Billion in annual revenues from chipsets and royalties from intellectual property.



Job Responsibilities:

· Drive design verification of DSP IP by working with a global DSP design team involving architecture, implementation, power, post silicon and back-end teams.

· Implement and improve System Verilog/UVM Testbench Architecture.

· Develop and deploy new verification methodologies, automation to continuously improve quality and efficiency.

· Develop design corresponding test plans, architect and develop verification environments, and meet coverage goals.

· Hands-on simulations and ability to debug not only IP level, but Subsystem and SoC level fails and bugs.

· Complete all required verification activities at IP level and ensure high quality commercial success of our products.

· Assertions, simulation, formal verification (static property checking), HW-SW co-verification, constraint/HVL-based verification, simulation acceleration, emulation are all tools you will use on a daily basis.

· Responsible gate level simulation bring-up, gate level verification with timing simulations.

· Responsible for power aware RTL verification and gate level simulation.

Skillset/Experience:

· 5-8 years experience in processor/ASIC design verification

· Solid background and understanding of Digital Design, Processor Architecture , Processor Verification and Power aware verification.

· Expertise in System Verilog Testbench Architecture and implementation.

· Experience in writing C based and assembly level testcases is preferred.

· Exposure to power aware implementation and verification using UPF is a plus.

· Experience with advanced verification techniques such as formal and assertions is a plus.

· Gate-Level Simulation and Debug "” 0-delay, timing annotated and power aware.

· Experience in System Verilog/UVM, and with simulators from Synopsys/Mentor/Cadence .

· Scripting/Automation Skills "” Perl, Python, Shell, Make file TCI .

· Solid analytical and debugging skills, strong knowledge of digital design and good understanding of Object Oriented Programming (OOP) concepts.

· Experience in Hardware verification languages (HVL) such as SystemVerilog testbench (OVM/UVM) and SystemC and Hardware description languages (HDL) such as Verilog, SystemVerilog is preferred.

· Experience in verification of Processor subsystems is preferred.

· Experience in creating validation suite and building automation.

· Should have excellent inter-personal and communication skills.

Minimum Qualifications:
"¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.

OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.