Job Area: Engineering Group, Engineering Group > Hardware Engineering
General Summary:
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.
Minimum Qualifications: "¢ Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
Serdes PHY Analog Design
Job Function
BDC SerDes Mixed-Signal design team is actively looking for
experienced (4-12+ years) analog circuit designers to work on
high speed SerDes PHYs. You will be directly involved in delivering next-generation custom PHY designs for SoCs and will be part of a growing team involved in architecture analysis in leading-nodes - finfets & beyond. Design goals include low-power analog designs to address Qualcomm's low-power wireless products.
Responsibilities
Hands-on experience - Analog circuit design
Experience in designing multiple analog building blocks - LDO, high speed TX and
RX (Equalizer, Sampler, PI, Deserializer etc) , Bias, Reference etc.
Analog and or Digital PLLs for frequency synthesis and/or SerDes applications"¯
Charge pump, loop filter, VCO/DCO, PFD/TDC, high speed dividers.
PLL Loop Dynamics, Jitter sources and modeling (RJ & DJ)
Ability to take a design, perform schematic to post layout verification, integration sign-off to post silicon bring up.
Work closely with RTL, DD, PD, DV and SoC verification teams to integrate the PHY.
Top Qualcomm Analog Design Engineer Interview Questions
Q1.Bridge and torch problem : Four people come to a river in the night. There is a narrow bridge, but it can only hold two people at a time. Th... read more