Principal Engineer - SoC Digital Verification

• Team leadership with technical guidance and tracking
• Verification planning.
• Verification test bench development, tuning and implementation.
• Development of verification test bench components such as drivers, monitors, response checkers as we'll as use most advanced UVM VIPs;
• Development of direct and constrained-random stimulus using c , SV
• Understands and analyzes RTL code, functional, assertion coverage results.
• Understands Develop functional coverage.
• Understands and develops system Verilog assertions.
• Understands and implements formal verification methods.
• Strong skills in debug, failure re-creation and root cause analysis
• Applicant should have efficient debugging and logic skills.

• C and UVM/SV based Test environment,
• Understanding of the design/architecture and ability to debug RTL/Gate netlist is MUST
• Coverage driven Verification for addressing Functional, Performance requirement of the SoC, regression management
• Microcontroller architecture, ARM Cores, Interconnect (NIC, FlexNoC), Cache Coherency,
• Bus Protocols like AHB/AMBA, AXI, ACE

Following skills will have additional value